Clock generation and clock recovery circuits typically use voltage-controlled oscillators (VCO's) within a phase lock loop (PLL) to either generate a clock from an external reference or from an incoming data stream. The overall performance of these circuits depends critically on the VCO, and excellent power supply rejection is a key requirement. This is especially important when the VCO is to be integrated onto a CMOS chip, such as a microprocessor, because CMOS logic generates large amounts of power supply noise when switching.
The usual measure of the VCO supply sensitivity is the frequency deviation per volt of power supply variation, relative to the VCO center frequency (% deviation/V). Previous work describes VCO and associated bias circuits which attain 0.7%/V supply sensitivity for a clock generation circuit, I. A. Young et al., "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors", IEEE J. Solid State Circuits, vol. 27, no. 11, pp. 1599-1607, although the temperature sensitivity is poor (4700 ppm/C) (where ppm is parts per million). Also known is a precision delay generator which can achieve only a 0.3%/V supply sensitivity, J. G. Manearis, et al., "Precise Delay Generation Using Coupled Oscillators", ISSCC 1993 Digest of Technical Papers, pp. 118-19, February 1993.
The present invention provides a bias generator scheme which allows for excellent power supply rejection, .ltoreq.0.1%/V, while maintaining very good temperature sensitivity, &lt;50 ppm/C.